Method of testing memory device, method of manufacturing memory device, apparatus for testing memory device, method of testing memory module, method of manufacturing memory module, apparatus for testing memory module and method of manufacturing computer

ABSTRACT

A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer. The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out from the measurement PC unit; a plurality of PFBs mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations. The PC tester is adapted to take out the signal from the chip set LSI on the PC mother board in the measurement PC unit to the individual memories on the memory module or the memory module per se and test them in quasi-operating conditions.

TECHNICAL FIELD OF THE INVENTION

[0001] This invention generally relates to the technology of testing andmanufacturing a memory device (which may be in the form of a chip or apackage) and a memory module. More particularly, the present inventionrelates to the technology that can effectively be used for a memory testsystem adapted to test an object of observation in quasi-operatingconditions typically by utilizing a personal computer.

BACKGROUND OF THE INVENTION

[0002] In the inventors' view, as a result of the recent technologicaldevelopments for achieving a larger memory capacity, the ability ofprocessing data having a greater bit width and a higher processing speedin the field of memory devices and memory modules, there is anever-increasing demand for memory test systems that can cope with theabove identified situation. Particularly, a memory device having a largememory capacity normally implies an increased test time and the abilityof processing data having a large bit width normally signifies a reducednumber of memory devices that can be tested at a time while a highprocessing speed refers to the requirement of the use of a higherfrequency and an improvement in terms of precision and quality.

[0003] Known memory test systems for testing semiconductor memoriesinclude general purpose memory testers adapted to both analyze and testmainly individual semiconductor memories and module testers adapted tocarry out a simple test only on memory modules. In other words,conventionally, a test apparatus adapted to a specific test object hasto be selectively used.

SUMMARY OF THE INVENTION

[0004] As a result of a series of analytical studies on known generalpurpose memory testers and module testers, the inventor of the presentinvention came to find as below. For example, general purpose memorytesters are highly functional but costly and it is difficult for them toproduce quasi-operating conditions by means of hardware and/or softwarebecause their functions are limited and the operating conditions quicklychange with time. On the other hand, module testers are less costly butlimited in terms test conditions and test types and hence they arepoorly convenient.

[0005] Meanwhile, manufacturers of personal computers and other dataprocessing apparatus comprising memory devices and/or memory modules areexperiencing inconveniences including that read/write operations do notproceed properly depending on the type and format and the supplier ofthe memory devices and/or the memory modules when randomly accessing amemory space under the control of a control circuit such as a CPU,although the memory devices and/or the memory modules must have passed atest. Thus, what the manufacturers are experiencing in reality is thatthe conventional testers have limits in terms of selecting good memorydevices and memory modules and quasi-operating conditions have to beprepared when testing them.

[0006] In view of the above circumstances, it is therefore an object ofthe present invention to provide a technique of testing andmanufacturing memory devices (which may be in the form of a chip of apackage) or memory modules that can highly reliably test them and selectgood ones in an inexpensive way.

[0007] The above and other objects and novelty features of the inventionwill become apparent in the following description made by referring tothe accompanying drawings.

[0008] Some of the various aspects of the present invention will besummarily described below.

[0009] In an aspect of the invention, there is provided a method oftesting a memory device by using a data processing unit having a memorydevice mounted thereon, said method comprising a step of supplying saidmemory device to be tested with a signal to be supplied said memorydevice and a step of checking the relationship between output signalsproduced from said memory device and output signals produced from saidmemory device to be tested.

[0010] With the above method of testing a memory device, a plurality ofsaid memory devices to be tested may be tested and said signals may besupplied in parallel to said plurality of memory devices to be tested.With the above method of testing a memory device, said data processingunit may have a control circuit connected to said memory device, saidcontrol circuit controlling an operation of said memory device. With theabove method of testing a memory device, said checking step is adaptedto check said output signals for agreement/disagreement. With the abovemethod of testing a memory device, said signals to be supplied to saidmemory device may include an address signal, a data signal, a clocksignal and a control signal. With the above method of testing a memorydevice, said signals supplied to said memory device to be tested may betransferred by means of a pipeline system. When said signals supplied inparallel to said plurality of memory devices to be tested may also betransferred by means of a pipeline system. Additionally, when aplurality of memory devices are to be tested, said signals supplied bymeans of said pipeline system may be distributed in a plurality ofstages and supplied in parallel to said plurality of memory devices tobe tested.

[0011] In another aspect of the invention, there is provided a method ofmanufacturing a memory device comprising a step of forming asemiconductor device having a memory, a step of supplying said memory ofsaid semiconductor device signals to be supplied to a first memorymounted on a data processing unit and checking the relationship betweensignals output from said first memory and signals output from saidmemory of said semiconductor device.

[0012] With the above method of manufacturing a memory device, aplurality of said memories used in said step of forming saidsemiconductor device may be formed and said signals to be supplied tosaid first memory may be supplied in parallel to said plurality ofmemories used in said step of forming said semiconductor device. Saiddata processing unit may be coupled to said first memory and has acontrol circuit for controlling an operation of said first memory. Saidchecking step may be adapted to check said output signals foragreement/disagreement. Said signals to be supplied to said first memorymay include an address signal, a data signal, a clock signal and acontrol signal.

[0013] In still another aspect of the invention, there is provided anapparatus for testing a memory device, said apparatus comprising asocket to be mounted with a memory device to be tested, a terminalsupplied from a data processing unit mounted with a memory with signalsto be supplied to the memory and output signals from said memory and acontrol section for determining relationship between output signals fromsaid socket and the output signals from said memory. The apparatus fortesting a memory device may comprise a first board for carrying saidsocket to be mounted with said memory device to be tested and a secondboard adapted to carrying a plurality of said first boards, distributethe signals to be supplied to said memory and supply the signals to saidmemory device to be tested. The apparatus for testing a memory devicemay comprise a plurality of types of said first boards to accommodatesaid memory device to be tested. Said memory device to be tested may bea TSOP or a TCP.

[0014] In said apparatus for testing a memory device, a plurality ofsaid memory devices to be tested may be tested and said signals to besupplied to said memory are supplied in parallel to said plurality ofmemory devices to be tested. Said data processing unit may be coupled tosaid memory and comprise a control connector for controlling anoperation of said memory. Said control circuit may be adapted to checksaid signals for agreement/disagreement. Said signals to be supplied tosaid memory may include an address signal, a data signal, a clock signaland a control signal. Said apparatus for testing a memory device mayfurther comprise a substrate for taking out the signal from the memorymounted on said data processing unit and supplying it to said terminal.

[0015] In still another aspect of the invention, there is provided amethod of testing a memory module by using a data processing unitmounted with a memory module having a plurality of memory devices, saidmethod comprising a step of supplying a memory device to be tested withsignals to be supplied to said memory module and a step of checkingrelationship between output signals from said memory module and theoutput signals from said memory device to be tested. Said memory modulemay be a DIMM.

[0016] With the method of testing a memory module, said signals to besupplied to said memory module are signals to be supplied to a firstmemory device of said plurality of memory devices and said outputsignals from said memory module are the output signals from a secondmemory device of said plurality of memory devices. Said first memorydevice and said second memory device may be a same memory device.

[0017] With the method of testing a memory module, a plurality of saidmemory devices to be tested may be tested and said signals to besupplied to said memory module may be supplied in parallel to saidplurality of memory devices to be tested. Said data processing unit maybe coupled to said memory module and have a control circuit forcontrolling the operation of said memory module. Said checking step maybe adapted to check said output signals for agreement/disagreement. Saidsignals to be supplied to said memory module may include an addresssignal, a data signal, a clock signal and a control signal. Said memorydevice to be tested may be one of a plurality of memory devices mountedon memory module.

[0018] In still another aspect of the invention, there is provided amethod of manufacturing a memory module comprising a step of preparing amemory device, a step of supplying said memory device from a dataprocessing unit mounted with a first memory with signals to be suppliedto the first memory and checking relationship between output signalsfrom said first memory and the output signals from said memory deviceand a step of forming the memory module by mounting on a substrate saidmemory device checked for the relationship in the preceding step. Saidmemory module may be a DIMM.

[0019] With said method of manufacturing a memory module, a plurality ofsaid memory devices may be prepared and said signals to be supplied tosaid first memory may be supplied in parallel to said plurality ofmemory devices. Said data processing unit may be coupled to said firstmemory and have a control circuit for controlling the operation of saidmemory module. Said checking step may be adapted to check said outputsignals for agreement/disagreement. Said signals to be supplied to saidfirst memory may include an address signal, a data signal, a clocksignal and a control signal.

[0020] In still another aspect of the invention, there is provided anapparatus for testing a memory module, said apparatus comprising a boardto be provided with a memory module having a plurality of memorydevices, a terminal supplied from a data processing unit mounted withsaid memory module with signals to be supplied to the memory module andwith output signals of said memory and a control section for supplyingsaid board with signals to be supplied to said memory module, and fordetermining relationship between output signals from said board andoutput signals from said memory module. Said memory module may be aDIMM.

[0021] In said apparatus for testing a memory module, said signals to besupplied to said memory module are signals to be supplied to a firstmemory device of said plurality of memory devices and said outputsignals from said memory module are output signals from a second memorydevice of said plurality of memory devices. Said first memory device andsaid second memory device may be a same memory device.

[0022] In said apparatus for testing a memory module, said signals to besupplied to said memory module may be supplied in parallel to saidplurality of memory devices. Said data processing unit may be coupled tosaid memory module and have a control circuit for controlling theoperation of said memory module. Said control section may be adapted tocheck said output signals for agreement/disagreement. Said signals to besupplied to said first memory may include an address signal, a datasignal, a clock signal and a control signal. Said apparatus for testinga memory module may be adapted to define a test unit on said board. Insaid apparatus for testing a memory module, one of said plurality ofmemory devices mounted on said memory module to be provided on saidboard may be tested.

[0023] In a further aspect of the invention, there is provided a methodof manufacturing a computer comprising a step of preparing a motherboard carrying a CPU, a socket to be mounted with a memory device to betested and a control circuit connected to said CPU and said socket, astep of preparing a memory module having a plurality of memory devicesand a step of arranging said memory module on said socket, said memorydevices of said memory module satisfying a predetermined relationship ina test step, said test step being adapted to supply signals from a dataprocessing unit mounted by a first memory to said memory devices, saidsignal being to be supplied to said first memory, and to checkrelationship between output signals from a first memory and outputsignals from said memory devices. Said memory module may be a DIMM.

[0024] In said apparatus for manufacturing a computer, said signals tobe supplied to said first memory may be supplied in parallel to saidplurality of memory devices. Said data processing unit may be coupled tosaid first memory and have a control circuit for controlling anoperation of said first memory. Said checking step may be adapted tocheck said output signals for agreement/disagreement. Said signals to besupplied to said first memory may include an address signal, a datasignal, a clock signal and a control signal.

[0025] Thus, with the method of testing a memory device, the method ofmanufacturing a memory device, the apparatus for testing a memorydevice, the method of testing a memory module, the method ofmanufacturing a memory module, the apparatus for testing a memory moduleand the method of manufacturing a computer according to the invention, amemory device or a memory module, whichever appropriate, can be testedin quasi-operating conditions. Additionally, according to the invention,it is now possible to realize a high performance test apparatus at lowcost by utilizing a personal computer comprising a data processing unit.Still additionally, according to the invention, it is now possible totest a memory device and a memory module. Still additionally, accordingto the invention, it is now possible to handle, simply by selectivelyusing a personal computer for testing, personal computers expected tohave only a short service life because of early model changes. Stilladditionally, according to the invention, it is now possible to test amemory device or a memory module including the performance of therelated peripheral circuits of the personal computer on which it is tobe mounted and the influence of processing operations of the personalcomputer using programs that could hitherto give rise to problems whenmounting it on the personal computer.

[0026] Some typical advantages that the present invention can provideinclude the following.

[0027] (1) Since the relationship between the output signal of thememory device or the memory module to be used as reference and theoutput signal of the memory device or the memory module, whicheverappropriate, to be tested, the memory chip (in the form of a chip), theunit product (in the form of a package), the memory module or thepersonal computer can be tested in quasi-operating conditions that arevery close to the actual operating conditions.

[0028] (2) Since a personal computer or the like comprising a dataprocessing unit having a control circuit for controlling the operationof the memory device or the memory module to be used as reference isutilized, it is possible to realized a high performance test apparatusat low cost.

[0029] (3) Since the data processing unit comprises a socket or the liketo which the memory device or the memory module to be tested is to bemounted and the socket may be selectively used, memory chips, unitproducts, memory modules and personal computers can be tested by meansof a same test apparatus.

[0030] (4) It is possible to handle personal computers expected to haveonly a short service life because of early model changes simply byselectively using a personal computer for testing comprising a dataprocessing unit mounted by a memory device or a memory module to be usedas reference.

[0031] (5) It is possible to test a memory device or a memory module inquasi-operating conditions, including the performance of the relatedperipheral circuits of the personal computer on which it is to bemounted and the influence of processing operations of the personalcomputer using programs that could hitherto give rise to problems whenmounting it on the personal computer.

[0032] (6) Since the signal supplied to the memory device or the memorymodule to be used as reference is supplied in parallel to a plurality ofmemory devices, a number of memory chips, unit products, memory modulesor personal computers can be tested simultaneously.

[0033] (7) Since a test method of checking the output signal of thememory device or the memory module to be used as reference and theoutput signal of the memory chip or the memory module, whicheverappropriate, to be tested for agreement/disagreement is applied to thestep of sorting memory chips, unit products or memory modules, the stepof carrying out an acceptance test on memory chips or unit productsand/or the step of carrying out an acceptance inspection on memorymodules, the high speed tester that has hitherto been used for them canbe replaced by a test apparatus according to the invention to reduce theinvestment for the test, the inspection and the manufacturing equipment.

[0034] (8) Memory chips, unit products and memory modules can be sortedunder quasi-operating conditions to consequently improve the quality ofmemory chips, unit products, memory modules and personal computers,since good products/no good products are sorted by checking the outputsignal of the memory device or the memory module to be used as referenceand the output signal of the memory chip, the unit product, the memorymodule, whichever appropriate, to be tested for agreement/disagreement.

BRIEF DESCRIPTIONS OF THE DRAWINGS

[0035]FIG. 1(a) shows a schematic front view of an embodiment of memorytest system according to the present invention, FIG. 1(b) a schematiclateral view of the memory test system of FIG. 1(a) and FIG. 1(c) aschematic perspective view of the memory test system of FIG. 1(a).

[0036]FIG. 2 is a schematic perspective view of the PC mother board ofthe embodiment of memory test system of FIG. 1.

[0037]FIG. 3 is a schematic block diagram of the PC mother board of theembodiment of memory test system of FIG. 1.

[0038]FIG. 4(a) is a schematic plan view and FIG. 4(b) is a schematiclateral view of the PFB (for a TSOP) of the embodiment of memory testsystem of FIG. 1.

[0039]FIG. 5(a) is a schematic plan view and FIG. 5(b) is a schematiclateral view of the socket board of the PFB (for a TSOP) of theembodiment of memory test system of FIG. 1.

[0040]FIG. 6(a) is a schematic plan view and FIG. 6(b) a schematiclateral view of the PFB (for a TCP) of the embodiment of memory testsystem of FIG. 1.

[0041]FIG. 7(a) is a schematic plan view and FIG. 7(b) a schematiclateral view of the socket board of the PFB (for a TCP) of theembodiment of memory test system of FIG. 1.

[0042]FIG. 8 is a schematic illustration of the signaling system of theembodiment of memory test system of FIG. 1.

[0043]FIG. 9 is a schematic illustration of the signaling system of theembodiment of memory test system of FIG. 1 when testing alone a memory.

[0044]FIG. 10 is a timing chart of the pipeline system to be used forthe embodiment of memory test system of FIG. 1.

[0045]FIG. 11 is a schematic illustration of the signal drawing outmethod to be used when testing alone a memory by the embodiment ofmemory test system of FIG. 1.

[0046]FIG. 12 is a schematic block diagram of the signal drawing outsubstrate of the embodiment of memory test system of FIG. 1.

[0047]FIG. 13 is a schematic block diagram of the control substrate ofthe embodiment of memory test system of FIG. 1.

[0048]FIG. 14 is a schematic block diagram of the distribution substrateof the embodiment of memory test system of FIG. 1.

[0049]FIG. 15 is a schematic block diagram of the PFB (distributingsection) of the embodiment of memory test system of FIG. 1.

[0050]FIG. 16 is a schematic block diagram of the PFB (socket section)of the embodiment of memory test system of FIG. 1.

[0051]FIG. 17 is a schematic illustration of the read/write switchingjudgment method to be used for the embodiment of memory test system ofFIG. 1.

[0052]FIG. 18 is a schematic illustration of the signaling system of theembodiment of memory test system of FIG. 1, when testing a memorymodule.

[0053]FIG. 19 is a is a schematic illustration of the signal drawing outmethod to be used when testing a memory module by the embodiment ofmemory test system of FIG. 1.

[0054]FIG. 20 is a flow chart of the testing step of the operation ofthe embodiment of memory test system of FIG. 1.

[0055]FIG. 21 is a flow chart of the step of mounting a module and aproduct of the operation of the embodiment of memory test system of FIG.1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] Now, a preferred embodiment of the present invention will bedescribed below by referring to the accompanying drawings. Throughoutthe drawings, same members are denoted respectively by the samereference symbols and will not be described repeatedly.

[0057]FIG. 1 schematically illustrates the embodiment of memory testsystem according to the invention, showing its appearance and FIGS. 2through 8 are schematic illustrations of the different components of theembodiment of memory test system. FIGS. 9 through 11 are schematicillustrations of the embodiment of memory test system when testing alonea memory and FIGS. 12 through 16 are schematic block diagrams of therespective substrates of the embodiment of memory test system. FIG. 17is a schematic illustration of the read/write switching judgment methodto be used for the embodiment of memory test system and FIGS. 18 and 19are schematic illustration of the signaling system of the embodiment ofmemory test system when testing a memory module. FIG. 20 is a flow chartof the testing step of the operation of the embodiment of memory testsystem and FIG. 21 is a flow chart of the step of mounting a module anda product of the operation of the embodiment of memory test system.

[0058] Firstly, the configuration of the embodiment of memory testsystem according to the invention will be described by referring toFIG. 1. FIG. 1(a) shows a schematic front view of an embodiment ofmemory test system according to the present invention and FIG. 1(b)shows a schematic lateral view of the memory test system, whereas FIG.1(c) shows a schematic perspective view of the memory test system. Thisembodiment of memory test system is a PC tester that is adapted toutilize personal computers and comprises a measurement PC unit 1 thatcarries a memory module to be used as reference; a signal distributionunit 2 for distributing the signal taken out of the measurement PC ofthe measurement PC unit 1; a plurality (herein, 16 pieces) of PFBs(performance boards) 3 mounted by respective objects of observation tobe observed simultaneously by using the signal distributed by the signaldistribution unit 2; a display panel 4 for displaying the current statusof the test that is being conducted; a power source 5 for producing theoperating voltage of the system and a control PC 6 for controlling theselection of test parameters and various analytical operations.

[0059] In the PC tester, the measurement PC unit 1, the signaldistribution unit 2, the PFBs 3, the display panel 4 and the powersource 5 are contained in a cabinet and only the control PC 6 isseparated from the cabinet. The PFBs 3 are housed in a constanttemperature tank 7 for producing actual operating conditions which isarranged to the left in the cabinet as viewed from the front side whilethe display panel 4 and the measurement PC unit 1 are locatedrespectively upper right and lower right in the cabinet. The signaldistribution unit 2 and the power source 5 are arranged respectivelybehind the display panel 4 and the measurement PC unit 1.

[0060] The measurement PC unit 1 carries a measurement PC 8 in theinside, which measurement PC 8 contains therein a data processing unitmounted with a memory module to be used as reference and, as shown inFIG. 2, typically comprises a CPU 12; memory slots 14 to be providedwith a memory modules 13; a chip set LSI 15 that is a control circuitconnected to both the CPU 12 and the memory slot 14; PCI slots 16 forinterfaces; secondary cache memories 17 and a power source 18 arrangedon the main surface of a PC mother board 11. The memory module 13exchanges signals with the CPU 12 under the control of the memorycontroller LSI called as chip set LSI 15. Thus, the chip set LSI 15practically controls the operation of the memory module 13 for assigningaddresses and also writing data to and reading data from the memorymodule 13. In other words, a test can be conducted in quasi-operatingconditions by taking out the signal transmitted from the chip set LSI 15to a single memory of the memory module 13.

[0061] On the PC mother board 11, the chip set LSI 15 is typicallyconnected to the CPU 12 by way of a host bus and to the memory module 13by way of a dedicated bus. The chip set LSI 15 is also connected to thePCI slots 16 by way of a PCI bus. Generally, the chip set LSI 15receives an instruction for reading data from the CPU 12, decodes theaddress contained therein so as to be able to access the memory module13 and sends the decoded address to the memory module 13. The read outdata is then sent from the memory module 13 to the CPU 12 by way of thechip set LSI 15. On the other hand, the data transmitted from theexternal device that is connected to the PCI slot 16 is forwarded to thechip set LSI 15 by way of the PCI bus and then decoded and written to anaddress of the memory module 13.

[0062] The signal distribution unit 2 operates as means for receivingthe signal taken out from the measurement PC 8 that is mounted with thememory module 13 to be used as reference and distributing it to the PFBs3. The signal taken out from the memory module 13 is buffered by thesignal drawing-out substrate and sent to the PFBs 3 by way of thedistribution board.

[0063] The PFBs 3 are DUTs (devices under test) that are operated in theoperating conditions same as those of the memory module in themeasurement PC unit 1 to be used as reference so that a number ofmemories to be observed can be tested simultaneously. FIGS. 4 through 7show typical PFBs. More specifically, FIGS. 4 and 5 show PFBs 3 forTSOPs (thin small outline packages) to be observed, while FIGS. 6 and 7show PFBs 3 for TCPs (tape carrier packages) to be observed. In FIGS. 4and 6, (a) is a schematic overall plan view and (b) is a schematicoverall lateral view, whereas, in FIGS. 5 and 7, (a) schematic plan viewand (b) is a schematic lateral view of the socket board of the PFBs.

[0064] Referring now to FIGS. 4 and 5, the PFBs 3 for TSOPs (memory ICs)to be observed comprise two kinds of boards, one of which are aplurality of (eight in FIG. 4) socket boards 22, each carrying aplurality of (eight in FIG. 4) IC sockets 21 on the main surface thereofthat are mounted by respective (eight) TSOPs, the other of which is amother board 24 carrying a plurality of ASICs 23 (application specificintegrated circuits) 23 to be used for distributing a signal andcomparing and judging the performance of the TSOPs on the main surfacethereof. The eight socket boards 22 and the single mother board 24 areconnected to each other by way of connectors 25 arranged on the rearsurfaces of the socket boards 22. The PFBs 3 having the configuration asshown in FIG. 4 are mutually connected by way of connectors 26. A totalof up to sixteen PFBs 3 can be contained in the constant temperaturetank 7 so that a total of up to (8×8×16)=1024 TSOPs can be observedsimultaneously.

[0065] Now, referring to FIGS. 6 and 7, the PFBs 3 for TCPs (memory ICs)to be observed also comprise two kinds of boards, one of which are aplurality of (eight in FIG. 6) socket boards 32, each carrying aplurality of (six in FIG. 4) IC sockets 31 on the main surface thereofthat are to be mounted with respective TCPS, and the other of which is amother board 34 carrying, on the main surface thereof, a plurality of(twenty eight) ASICs 33 to be used for distributing a signal andcomparing and judging the performance of the TCPs. The eight socketboards 32 and the single mother board 34 are connected to each other byway of connectors 35 arranged on the respective rear surfaces of theboards. The PFBs 3 having the configuration as shown in FIG. 6 aremutually connected by way of connectors 36. A total of up to sixteenPFBs 3 can be contained in the constant temperature tank 7 so that atotal of up to (6×8×16)=768 TCPs can be observed simultaneously.

[0066] The display panel 4 operates to display the current status of thetest that is being conducted and the operating conditions of themeasurement PC unit 1 in such a way that the testing operator canvisually recognize them.

[0067] The power source 5 produces the voltage necessary for driving thePC tester. More specifically, it is used to drive the respectiveinternal component units of the PC tester. Additionally, different testscan be conducted by varying the voltage produced by the power source 5.

[0068] The control PC 6 contains in it a control substrate forcontrolling the selection of test parameters and various analyticaloperations so that the start and the end of each test is also controlledby the control substrate.

[0069] Now, the signaling system of the PC tester having the abovedescribed configuration will be described by referring to FIG. 8. Asshown in FIG. 8, the signaling system of the PC tester comprises asignal drawing-out substrate 41 for taking out a signal from the memorymodule 13 in the measurement PC unit 1 and buffering it; a controlsubstrate 42 contained in the control PC 6 and adapted to output acontrol signal for the start or the end of a test; two-stagedistribution substrates 43 (one board on the first stage and threeboards on the second stage) contained in the signal distribution unit 2and adapted to distribute the signal buffered by the signal drawing-outsubstrate 41; and a plurality of ( sixteen in FIG. 8) PFBs 3 to whichthe signal is distributed by the distribution substrates 43. The voltagenecessary to drive the PFBs 3 is supplied from the power source 5.

[0070]FIG. 9 shows an operation of the signaling system in a testingoperation using the PC tester. Referring to FIG. 9, the signal drawingout substrate 41 draws out a signal from the memory module 13 arrangedon the PC mother board 11 in the measurement PC unit 1 and buffers it.The buffered signal is then distributed by the first stage and secondstage distribution substrates 43 having flip-flop circuits (F/Fs) 51 forpipeline data transfer and a distribution circuit 52. The distributedsignal is then sent to the PFBs, each comprising flip-flop circuits(F/Fs) 53 for pipeline data transfer, a command analysis/applicationcontrol (R/W) circuit 54, a judgment circuit 55 and a judgment resultoutput register (P/F: pass/fail) 56, which PFBs then test the memories57 to be observed such as TSOPs or TCPs that are mounted on the ICsockets 21 or 31, whichever appropriate. Signals such as an addresssignal, a clock signal, a control signal and so on are applied to thememories 57 to be observed by the corresponding PFB 3, which is by turnadapted to exchange data and other signals with the memories 57 to beobserved. A pass/fail signal is taken out from the register 56 of thePFB 3 to show the result of the test.

[0071] Data can be transferred at high speed for the above signalingsystem by means of a pipeline system, which is a system forsynchronizing signals, while latching data among circuits by means ofthe flip-flop circuits 51, 53, and transferring them at high speed. Thefrequency of exchanging clock signals between the flip-flop circuits 51,53 needs to be higher than the rate of signal transmission. The clocksignal of the memory module 13 to be used as reference such as that ofthe SD-RAMs (synchronous dynamic random access memories) of a DIMM (dualin-line memory module) is typically used for the purpose of theinvention. Therefore, the flip-flop circuits for the pipeline arearranged at the input stage and the output stage of each substrate inorder to absorb variances that arise to signal transmission.

[0072] With the pipeline system, as shown in FIG. 10 (timing chart forthe operations indicated respectively by (1) through (4) in FIG. 9),signal n for the operation of the DIMM is delayed by two cycles at theoutputs of the first stage distribution substrate 43, also by two cyclesat the outputs of the second stage distribution substrates 43 and thenby two cycles relative to the memories 57 to be observed so that it isdelayed by six cycles for transmission from the start of the operationof the DIMM to time of the application thereof to the memories 57 to beobserved. While the signal n is delayed by six cycles for the memories57 to be observed of the first stage, it is delayed further for thememories 57 to be observed of the second stage for the purpose ofreducing the power consumption rate at peak periods. Therefore, with thepipeline operation system, the cycle of operation is temporally shiftedrelative to the operation of the DIMM during the test. Thus, while thecycle of operation of the memories 57 to be observed is delayed fromthat of the DIMM to be used as reference by a time corresponding to thenumber of stages of the pipeline, the speed and pattern of operation inthe same condition as the DIMM to be used as reference can bemaintained.

[0073] During the test, a signal is taken out from the DIMM 61 that isthe memory module mounted on the PC mother board 11 as shown in FIG. 11,which schematically illustrates the signal drawing out method to be usedwhen testing alone a memory by the embodiment of memory test system.Referring to FIG. 11, the signal sent from the chip set LSI 15 to theDIMM 61 is taken out from a selected one of the SD-RAMs 62, which arememory ICs, on the DIMM 61 in order to conduct the test in conditionssame as the actual operating conditions. As shown in FIG. 11, a wire issoldered to the selected SD-RAM 62 and the signal is directly drawn outof the SD-RAM 62 and quickly buffered by the signal drawing-outsubstrate 41. With this technique of drawing out the signal, theinfluence of degradation of the signal waveform and that of reflectionto the original SD-RAM 62 can be minimized.

[0074] Now, the functional blocks of the substrates of the signalingsystem of the PC tester shown in FIGS. 8 and 9 will be described indetail by referring to FIGS. 12 through 16. FIG. 12 through 14respectively illustrate the functional blocks of the signal drawing outsubstrate 41, the control substrate 42 and the distribution substrate43, whereas FIGS. 15 and 16 schematically illustrates the functionalblock of the PFBs 3. More specifically, FIG. 15 shows the distributionsections of the PFBs 3 and FIG. 16 shows the socket sections (for twosockets) of the PFBs 3.

[0075] As shown in FIG. 12, the signal drawing-out substrate 41 isadapted to receive the signal taken out from the selected SD-RAM 62 onthe DIMM 61 to be used as reference on the PC mother board 11 of themeasurement PC 8 at the input terminal thereof and typically processaddress signal Add, control signal Cont and data signal Data at signalblocks 1 through n and clock signal Clk at a clock signal block beforeoutputting the processed signals through the respective outputterminals.

[0076] The signal blocks 1 through 1 for the address signal Add, thecontrol signal Cont and the data signal Data comprises respectiveflip-flop circuits FF111 through FFn11 and FF112 through FFn12 arrangedat the input stages and the output stages for the purpose of pipelinedata transfer and differential drivers DD111 through DDn11. The addresssignal Add, the control signal Cont and the data signal Data that areinput are then latched by the flip-flop circuits FF111 through FFn11 andFF112 through FFn12 in synchronism with the reference clock signal andthe variances, if any, among the signal blocks are corrected andsynchronized before they are output as proper/inverted signals by way ofthe differential drivers DD111 through DDn11.

[0077] The clock signal block for the clock signal Clk comprises a clockgenerating circuit for waveform shaping; a timing regulating circuit fortiming regulation; and a differential driver D11. The input clock signalClk is shaped in terms of waveform by the clock generating circuit andmade to become reference clock signal for the flip-flop circuits FF111through FFn11 and FF112 through FFn12 of said signal blocks 1 through n.At this time, it is delayed by several cycles from the signal of theDIMM 61 to be used as reference. Additionally, the clock signal Clk isregulated in terms of timing by the timing regulating circuit andsynchronized with the operation of said signal blocks 1 through n beforeit is output as proper/inverted clock signal by way of the differentialdriver DD11.

[0078] The signal drawing-out substrate 41 is provided with adifferential receiver DR11 for receiving a low speed BUS (bus) signal asinput, a low speed BUS control signal and a control register. As the lowspeed BUS signal is input from the control PC 6 by way of thedistribution substrates 43, it is received by the differential receiverDR11 and applied to the clock generating circuit and the timingregulating circuit of the clock signal block by way of the low speed BUScontrol circuit and the control register for the purpose of timingregulation. The substrate numbers are also supplied to the low speed BUScontrol circuit.

[0079] As shown in FIG. 13, the control circuit 42 is connected to AT(asynchronous transfer) BUS of the control PC 6 and comprises anATBUS-I/F (interface)/address decode/I/O (input/output) address decodecircuit, a flag circuit (I/O address); an address control circuit; adata memory; a low BUS control circuit; a power source control circuit;a differential driver DD21; and a differential receiver DR21. An addresssignal is input to the ATBUS-I/F (interface)/address decode/I/O(input/output) address decode circuit by way of ATBUS and the flagcircuit and the address control circuit can exchange signals with ATBUS.

[0080] The address signal input to the ATBUS-I/F (interface)/addressdecode/I/O (input/output) address decode circuit is decoded and theaddress control circuit controls read/write operations relative to thedata memory according to the decoded address signal. The low speed BUScontrol circuit outputs a low speed BUS signal by way of thedifferential driver DD 21 for the purpose of timing regulation of thereference clock signal at the signal drawing out substrate 41 and thedistribution substrates 43, and receives another low speed BUS signalcontaining a judgment signal representing the result of judgment fromthe PFBs by way of the differential receiver DR21 in order to determinepass/fail of each memory 57 to be observed. The low speed BUS signal isused as interrupt signal for controlling the analysis function at thetime of self-diagnosis and debugging. Additionally, a power sourceON/OFF signal is output from the power source control circuit to thepower source.

[0081] As shown in FIG. 14, the distribution substrates 43 receiveaddress signal Add, control signal Cont, data signal Data and clocksignal Clk from the signal drawing out substrate 41 by way of the inputterminals and receive a low speed BUS signal from the control substrate42 also by way of the input terminals. The address signal Add, thecontrol signal Cont and the data signal Data are processed in the signalblocks 1 through n and the clock signal Clk is processed in the clocksignal block, whereas the low speed BUS signal is processed in the lowspeed BUS block before they are output through the respective outputterminals.

[0082] The signal blocks 1 through n for processing the address signalAdd, the control signal Cont and the data signal Data respectivelycomprise differential receivers DR131 through DRn31 arranged at theinput stage; flip-flop circuits FF131 through FFn31 also arranged at theinput stage for the purpose of pipeline data transfer; multiplexersMUX131 through MUXn31 for switching from the normal operation to theoperation of the low speed BUS signal or vice versa; a plurality (six inFIG. 14) of flip-flop circuits FF132 through FFn32 arranged at theoutput stage and adapted to both transfer and distribute data by meansof the pipeline system; and a plurality of (six in FIG. 14) differentialdrivers DD131 through DDn31 arranged at the output stage. As the addresssignal Add, the control signal Cont and the data signal Data are inputby way of the differential receivers DR131 through DRn31, they arelatched by the flip-flop circuits FF131 through FFn31 at the input stagein synchronism with the reference clock signal, selected by themultiplexers MUX131 through MUXn31 and latched again by the flip-flopcircuits FF132 through FFn32 at the output stage in synchronism with thereference clock signal. Then, the variances of the signals among thesignal blocks as well as among distributions in the respective signalblock are corrected and the signals are synchronized before they areoutput as proper/inverted signals by way of the differential driversDD131 through DDn31. Note that the signals are distributed to the sixdifferential drivers of the respective signal blocks.

[0083] The clock signal block for the clock signal Clk comprises adifferential receiver DR31 arranged at the input stage; a clockgenerating circuit for waveform shaping; a timing regulating circuit fortiming regulation and a plurality of (six in FIG. 14) differentialdrivers DD31 arranged at the output stage. As the clock signal Clk isreceived by the differential receiver DR31, it is shaped in terms ofwaveform by the clock generating circuit and made to become referenceclock signal for the flip-flop circuits FF131 through FFn31 and FF132through FFn32 of said signal blocks 1 through n. Additionally, the clocksignal Clk is regulated in terms of timing by the timing regulatingcircuit and synchronized with the operation of said signal blocks 1through n before it is output as proper/inverted clock signaldistributed in six routes by way of the differential drivers DD31.

[0084] The low speed BUS signal block for the low speed BUS signalcomprises a differential receiver DR32 arranged at the input stage; aplurality of (six in FIG. 14) differential drivers DD32 arranged at theoutput stage; and a differential driver DD33 for outputting signals tothe signal drawing-out substrate 41. As the input low speed BUS signalis received by the differential receiver DR32, it is output asproper/inverted low BUS signal distributed in six routes by way of thedifferential drivers DD32. Further, the low BUS proper/inverted signalis also output to the signal drawing-out substrate 41 by way of thedifferential driver DD33.

[0085] The distribution substrates 43 additionally comprise a low speedBUS control circuit adapted to receive a low speed BUS signal as inputand a pair of control registers. As the low speed BUS signal is inputfrom the control substrate 42, it is sent to the clock generatingcircuit of the clock signal block by way of one of the control registerand used to regulate the reference clock signal in terms of timing whileit is also sent to the timing regulating circuit for timing regulationby way of the other register. It is also possible to use themultiplexers MUX131 through MUXn31 of the signal blocks 1 through n forswitching from the normal operation to the operation of the low speedBUS signal or vice versa. Note that the substrate numbers are alsosupplied to the low speed BUS control circuit.

[0086] The first stage and the second stage of the above describeddistribution substrates 43 have a similar circuit configuration. Thesignal drawn out from the DIMM 61 to be used as reference by way of thesignal drawing out substrate 41 is distributed to the six distributionroutes at the first stage and then to the six distribution routes of thepaired distribution substrates of the second stage and to the fourdistribution routes of the single distribution substrate of the secondstage. Thus, with the pipeline system, it is possible to distribute theinput signal to a total of sixteen different routes before it gets tothe PFBs 3 of the subsequent stage without changing the speed andpattern of operation of the DIMM to be used as reference in order torealize a high speed signal transmission. Note that the distributionsubstrates 43 also comprise a control circuit for testing signal “Pass”in the distribution circuit.

[0087] Now, referring to FIGS. 15 and 16, the address signal Add, thecontrol signal Cont, the data signal Data and the clock signal Clk areinput from the distribution substrates 43 of the second stage to thedistributing sections of the PFBs 3 as shown in FIG. 15, and the addresssignal Add, the control signal Cont and the data signal Data areprocessed in the signal blocks 1 through n, while the clock signal Clkis processed in the clock signal block before they are output to therespective socket sections of the PFBs 3.

[0088] The signal blocks 1 through n for processing the address signalAdd, the control signal Cont and the data signal Data respectivecomprise differential receivers DR141 through DRn41 arranged at theinput stage; flip-flop circuits FF141 through FFn41 for pipeline datatransfer also arranged at the input stage; and a plurality of (four inFIG. 15) drivers D141 through Dn41 to be used for distribution. As theaddress signal Add, the control signal Cont, the data signal Data arereceived by the differential receivers DR141 through DRn41 as inputsignals, they are latched by the flip-flop circuits FF141 through FFn41of the input stage in synchronism with the reference clock signal andoutput through the drivers D141 through Dn41 Note that the outputsignals are distributed to the four differential drivers of the signalblocks.

[0089] The clock signal block for processing the clock signal Clkcomprises a differential receiver DR41 arranged at the input stage; aclock generating circuit for waveform shaping; and a plurality of (fourin FIG. 15) drivers to be used for distribution. As the clock signal Clkis received by the differential receiver DR41 as input signal, it isshaped by the clock generating circuit in terms of waveform and turnedto reference clock signal for the flip-flop circuits FF141 through FFn41of the signal blocks 1 through n before it is output through the driversD41. Note that the clock signal is distributed to the four drivers D41of the clock signal block.

[0090] The distributing section of the PFBs 3 comprises a commandanalysis/judgment/I/O control circuit adapted to receive the controlsignal Cont and the reference clock signal as input; a plurality of(four in FIG. 16) drivers D42 for distributing the I/O control signal;and a plurality of (four in FIG. 16) drivers D43 for distributing thejudgment signal. The input command is analyzed by the commandanalysis/judgment/I/O control circuit on the basis of the control signalCont to generate an I/O control signal for read/writing operation and ajudgment signal for starting a judgment operation, of which the I/Ocontrol signal is distributed in four routes by way of the drivers D42and output, while the judgment signal is also distributed in four routesby way of the drivers D43 and output.

[0091] The address signal Add, the control signal Cont, the data signalData, the clock signal Clk, the I/O control signal and the judgmentsignal output from the distributing section of the PFBs 3 are then inputto the socket section (for two sockets) of the PFBs 3 respectively,which will be described hereinafter by referring to FIG. 16. Note that{circle over (1)} through {circle over (5)} shown at the output stage ofFIG. 15 and those shown at the input stage of FIG. 16 indicate theconnection between the respective signal transmission routes.

[0092] As shown in FIG. 16, the address signal Add, the control signalCont, the data signal Data, the clock signal Clk, the I/O control signaland the judgment signal are input from the distribution section of thePFBs 3 to the socket section (for two sockets) of the PFBs 3 while thelow speed BUS signal is input from the distribution substrates 43 of thesecond stage through the input terminal. Of the input signals, theaddress signal Add and the control signal Cont are processed by the twodistribution blocks of the input system and the data signal Data isprocessed by the three distribution blocks of the data system, whereasthe clock signal Clk, the I/O control signal, the judgment signal andthe low speed BUS signal are processed respectively by the clock signalblock, the IO control block, the judgment block and the low speed BUSblock before they are output through the respective output terminals.

[0093] The two distribution blocks of the input system for receiving theaddress signal Add and the control signal Cont comprise a plurality of(two in FIG. 16) flip-flop circuits FF51 arranged at the output stagefor pipeline data transfer and signal distribution; and a plurality of(two in FIG. 16) drivers D51 also arranged at the output stage. Theaddress signal Add and the control signal Cont that are received asinput are latched by the flip-flop circuits FF51 in synchronism with thereference clock signal and the variances, if any, of distributionbetween and in the two distribution blocks of the input system arecorrected before they are synchronized and distributed in two routes byway of the two drivers D51. The address signal Add and the controlsignal Cont distributed to the two drivers D51 are then supplied to thegauge memories (DUT1, DUT2) 57 mounted on the IC sockets 21 on the onehand and to the ASICs 23, 33 of the subsequent step on the other.

[0094] The three distribution blocks of the data system for receivingthe data signal Data comprise a plurality of (three in FIG. 16)flip-flop circuits FF52 arranged at the output stage for both pipelinedata transfer and signal distribution; a plurality of (three in FIG. 16)drivers D52 also arranged at the output stage; a plurality of (two inFIG. 16) receivers R51 arranged at the input stage; a plurality of(three in FIG. 16) switches 51 for isolating the output of the driversD51; a logic circuit including a plurality of (five in FIG. 16)flip-flop circuits F53 through FF55, a plurality of (two in FIG. 16)exclusive OR gates EXOR51 and a plurality of (two in FIG. 16) OR gatesOR51 for comparing the expected value and the observed value (read outdata) and judging the observed value for pass/fail, and an expectedvalue delay circuit.

[0095] When writing data, the input data signal Data are latched by theflip-flop circuits FF52 in synchronism with the reference clock signaland the variances, if any, of distribution between and in the threedistribution blocks of the data system are corrected so that they aresynchronized and distributed to the three drivers D52. The data signalData distributed to the three drivers D52 are then supplied to the gaugememories 57 mounted on the two IC sockets 21 and the ASIC 23, 33 of thesubsequent step so as to be written in the gauge memories 57 as writtendata.

[0096] When reading data, the data signal Data read out from the gaugememories 57 mounted on the two IC sockets 21 are received by thereceivers R51 and latched by the flip-flop circuits FF53 in synchronismwith the reference clock signal, while the data signal Data inputsimultaneously to make an expected value is delayed by the expectedvalue delay circuit and latched by the flip-flop circuits F55 insynchronism with the reference clock signal. Then, the read out data andthe expected value are respectively compared by the exclusive OR gatesEXOR51. The signals representing the result of the comparison aresubjected to an OR operation at the respective OR gates OR51, using thefeedback signals output from the flip-flop circuits FF54 so thatultimately agreement/disagreement signals (agreement: Low, disagreement:High) are latched by the respective flip-flop circuits FF54 and outputto the low speed BUS block.

[0097] The clock signal block for processing the clock signal Clkcomprises a clock timing generating circuit for waveform shaping and, aplurality of (three in FIG. 16) distribution drivers D53. The inputclock signal Clk is regulated for waveform by the clock timinggenerating circuit so as to be used as reference clock signal for theflip-flop circuits FF51, FF52, FF54, FF56 and FF57, which are partlydescribed above and will be partly described hereinafter, and for astrobe monitoring circuit, which will be described hereinafter, and thendistributed to three routes by way of the drivers D53. The clock signalClk distributed to three routes are then supplied to the gauge memories57 mounted respectively on the paired IC sockets 21 and also to theASICs 23, 33 of the subsequent step.

[0098] The I/O control block for processing the I/O control signalcomprises a plurality of (two in FIG. 16) flip-flop circuits FF56arranged at the output stage and adapted to both pipeline data transferand distribution; and a driver D54 also arranged at the output stage. Asthe I/O control signal is input, it is latched by the flip-flop circuitsFF56 in synchronism with the reference clock signal and the switch S51is connected for write operation and disconnected for read operation bythe output of one of the flip-flop circuits FF56 while the output of theother flip-flop circuit FF56 is supplied to the ASICs 23, 33 of thesubsequent stage by way of the driver D54.

[0099] The judgment block for processing the judgment signal alsocomprises a plurality of (two in FIG. 16) flip-flop circuits FF57arranged at the output stage and adapted to both pipeline data transferand distribution; a driver D55 also arranged at the output stage; and astrobe monitoring circuit for the prevention of misjudgment. As thejudgment signal is input, it is latched by the flip-flop circuits FF57in synchronism with the reference clock signal and the output of one ofthe flip-flop circuits is used as reference clock signal for saidflip-flop circuits FF53, FF55 for the purpose of comparing the expectedvalue and the observed value and judging the observed value forpass/fail, the strobe monitoring circuit being used to monitor thejudgment signal, whereas the output of the other flip-flop circuit FF57is supplied to the ASICs 23, 33 of the subsequent step by way of thedriver D55. The status signal for starting a judgment operation that ismonitored by the strobe monitoring circuit is output to the low speedBUS block.

[0100] The low speed BUS block for processing the low speed Bus signalcomprises a low speed BUS control circuit and a driver D56. As the lowspeed BUS signal is input, it is supplied to the ASICs 23, 33 of thesubsequent step by way of the low speed BUS control circuit and thedriver D56. The low speed BUS control circuit is adapted to receive theagreement/disagreement signal input from the flip-flop circuits FF54 ofthe three distribution blocks of the data system and receive the statussignal for starting a judgment operation input from the strobemonitoring circuit of the judgment block. The reliability of theagreement/disagreement (pass/fail) signal is verified in the read mode.

[0101] As described above, the PFBs 3 having a distribution section anda socket section comprise a circuit for distributing the signal from thedistribution substrates 43 that is equivalent to the signal of the DIMM61 to four routes and supplying it to the memories 57 to be observed;and a circuit for analyzing the command representing the status ofoperation of the SD-RAMs 62 on the basis of the control signal containedin the distributed signal so that they judge for read or write operationand; if the SD-RAMs 62 are being used for write operation, they use theinput/output signal as signal to be applied to the memories 57 to beobserved; whereas in reading operation they use the input/output signalas signal representing the expected value to be used for the judgment ofthe input/output signal. The operation of the PFBs are controlled by thehardware. They further comprise a circuit for logically comparing theoutput signal from each of the memories 57 to be observed and theexpected value at the judgment circuit; and a circuit for judging forpass/fail. The above circuits are used to constitute the ASICs 23, 33 onthe basis of a unit of 2 duts and signals are transmitted to 2 duts ofthe ASICs 23, 33 of the subsequent stage by means of the chain system sothat a chain is adapted to accommodate 16 duts. In this way, a PFB canobserve a total of 64 duts, or 16 duts×16 distribution routes,simultaneously.

[0102] Now, the method of switching read/write operation and judging forpass/fail will be summarily described by referring to FIG. 17. As shownin FIG. 17, signal application control/judgment hardware is formed bythe circuits on each substrate, said hardware comprising an address Bitcontrol circuit, a control Bit analysis circuit; a data Bit controlcircuit; a signal application/judgment switching circuit; and a judgmentcontrol circuit. The SD-RAMs 62 on the DIMM 61 are controlled byaddress, input/output data and control signals as described above andthe data input/output operation is controlled by a control signal.

[0103] Therefore, a circuit for analyzing the above control operationsis installed. The address signal is supplied to the memories 57 to beobserved by way of the address Bit control circuit and the controlsignal is supplied to the memories 57 to be observed by way of thecontrol Bit control circuit, while (1) the control signal transmittedfrom the SD-RAMs of the DIMM 61 to be used as reference is analyzed bythe control Bit analysis circuit to recognize any data input/output. (2)Then the application of data to or the output of data from the memories57 to be observed is selected by the application/judgment switchingcircuit corresponding to the data input/output. In the write mode, thedata transmitted from the SD-RAMs 62 of the DIMM 61 to be used asreference is written to the memories 57 to be observed by way of thedata Bit control circuit and the application/judgment switching circuit.(3) In the read mode, on the other hand, the signal from the SDRAMs 62is received from the data Bit control circuit as expected value, and thejudgment control circuit compares the expected value and the data readout from the memories 57 to be observed by way of theapplication/judgment switching circuit in order to judge if the memories57 to be observed output signals that are equivalent to that of the DIMM61 to be used as reference.

[0104] The operation of the signaling system when testing memory modulesin place of single memories as described above by referring to FIG. 9will be now discussed below by referring to FIG. 18. As shown in FIG.18, the signal of the DIMM 61 mounted on the PC mother board 11 in themeasurement PC unit 1 is taken out and buffered by means of the signaldrawing out substrate 41. The buffered signal is then distributed bymeans of the distribution substrates 43 having flip-flop circuits anddistribution circuits for pipeline data transfer. The distributed signalis then transmitted to the PFBs 3 having flip-flop circuits for pipelinedata transfer and command analysis, signal control and datacomparison/judgment circuits and the memory modules 71 to be observedsuch as DIMMs on the PFBs 3 are tested. Signals such as an addresssignal and a clock signal can be applied to the memory modules 71 to beobserved by the PFBs 3, which are adapted to exchange data. The resultof the observation is taken out from the PFBs 3 to the control PC 6 bythe control IF pass/fail read circuit.

[0105] For a test, the signals of the DIMM 61 mounted on the PC motherboard 11 as shown in FIG. 19 is taken out. As in the case of testingsingle memories, signals are taken out from the DIMM 61 from the chipset LSI15 in order to produce the operating conditions. As shown in FIG.19, all the signals of the DIMM 61 are take out by way of wires andimmediately buffered by the signal drawing out substrate 41. With thismethod of taking out signals, the influence of degradation of the signalwaveform and that of reflection to the original DIMM 61 can beminimized.

[0106] As described above, when memory modules are selected as objectsof test in place of single memories, all the signals that are input toand output from each module are controlled for observation, disregarding1 dut of the memory to be used as reference. Therefore, while the unitto be used for the judgment of pass/fail is shifted from a memory to amodule, the same control techniques and the same hardware configurationcan be used. It is also possible to identify any defective memories in amemory module by controlling the operating conditions of the DIMM 61 tobe used as reference and controlling the memories of the memory moduleon a memory by memory basis (by assigning I/O) so that a specific memorymay be exclusively tested.

[0107] Now, the flow of the operation of testing a memory chip, a unitproduct (in the form of a package) or a memory module will be describedby referring to FIG. 20. For the test process, single memories 57 to beobserved such as TSOPs or TCPs are mounted on the IC sockets 21 of thePFBs 3 as described above while memory modules 71 to be observed such asDIMMs are used with PFBs 3 provided with sockets for receiving modules.

[0108] Firstly, a wafer carrying a plurality of memory circuits as chipsis brought in and a probe test (P test) is conducted to test theelectric characteristics of the memory circuits on the wafer. Thedefective chips, if any, as detected by the probe test are remedied andrelieved by using redundant memory cells and/or signal lines (Steps S101through S103).

[0109] Then, after dicing the wafer to produce isolated chips andassembling them to so may unit packages, they are treated in a burn-in(B/I) step where a rated voltage or a voltage higher than the ratedvoltage is applied to each memory to be observed at predeterminedtemperature so that the packages are screened while a signal is beingapplied to the memory circuits in quasi-operating conditions (StepS104).

[0110] Subsequently, the individual memories are tested by means of thePC tester of this embodiment (Steps S105, S106). In this test step, thememories are subjected to a long test where the memory circuits aretypically disturbed by using a frequency longer than the ordinaryfrequency, and a function test where the memories are tested for theirfunctions by driving them for read/write operations, using apredetermined test pattern to confirm that they properly operate.

[0111] Thereafter, the memories are tested firstly in a DC test step foropen/short test between the input terminal and the output terminal, leakcurrent test and source current test (in operation and in the stand-bystate) by using an ordinary memory tester and then in a timing test stepfor AC timings including setup and hold when exchanging signals with thechip set LSI 15 (Steps S107, S108). After the completion of this teststep, individual packages that are judged to be good can be shipped asproducts (Step S109).

[0112] The above steps are applicable not only to individual products inthe form of packages as described above but also to memory chips thatare produced by dicing a wafer or even those that are still in the formof a wafer that is to be diced so that good memory chips may be shippedafter the test steps. It will be appreciated that the operation ofassembling memory chips into a package can be eliminated before theburn-in process if the memory chips are tested per se. If, on the otherhand, memory chips are tested in the form of a wafer, the steps from theburn-in process are followed and the wafer is diced into memory chipsafter the timing test.

[0113] Additionally, a plurality of memory chips that are judged to begood may be mounted on a module substrate to produce a memory modulesuch as a DIMM, which is then subjected to a simple test conducted tofind it as good or no good so that it may be shipped as memory moduleproduct if it is found to be a good one (Steps S110 through 112). It maybe needless to say that a plurality of memory chips are assembled into amemory module for shipment.

[0114] Thus, while, conventionally, memory chips that come out of aburn-in process are subsequently subjected to a series of testsincluding a long test, a DC test, a function test and a timing test andassembled into modules, which are then screened typically by using a PCbefore shipment, with the above described embodiment, memory chips aretested by a PC tester according to the invention for a long test and afunction test before a DC test and a timing test that are conducted bymeans of an ordinary memory tester in a conventional way. Thus, thisembodiment can reduce the time required for the test using a memorytester by half. Additionally, a PC tester according to the invention cantest a large number of (k) memory chips simultaneously if compared witha conventions tester that can test only 64 memory chips at a time sothat the present invention can remarkably reduce the overall test time.

[0115] Now, the operation of mounting a memory module on a PC will bebriefly described by referring to the flow chart of FIG. 21. Themanufacturer of individual memory chips carries out a screening test byusing a PC tester on products that may be in the form packages or memorychips and good ones obtained as a result of the screening test areshipped as good ones (Steps S201, S202). Thus, the manufacturer ofindividual memory chips utilizes the embodiment of PC tester for thescreening test.

[0116] Subsequently, the module assembler carries out a receiving teston the packages or the memory chips shipped from the manufacturer ofindividual memory chips (Step S203) and then sends them to the assemblyline. On the assembly line, a pattern is printed on a module substrateby using creamy solder and memory chips or packages are mounted thereonalong with other components before they are thermally treated byreflowing in order to electrically connect the module substrate and thecomponents on it (Steps S204 through S206). Thereafter, the memorymodule is tested for appearance and marks are applied to it before it issubjected to a screening test for finding it is good or no good so that,if it is found to be a good one, it may be shipped as memory moduleproduct (Steps S207 through S210). The module assembler utilizes theembodiment of PC tester for the receiving test and/or the screeningtest.

[0117] Then, the PC manufacturer carries out a receiving test on thememory modules shipped from the module assembler and mounts them on PCproducts (Steps S211, S212). In this mounting process, the PCmanufacturer carriers out a test on the PC products so that the PCproducts that have passed the test can be shipped as final products(Steps S213, S214). Thus, the PC manufacturer utilizes the embodiment ofPC tester for the receiving test.

[0118] Thus, the above described embodiment of PC tester comprises ameasurement PC unit 1 that carries a memory module to be used asreference; a signal distribution unit 2 for distributing the signaltaken out of the devices PC8 to be observed; a plurality of PFBs 3mounted by respective objects of observation to be observedsimultaneously by using the signal distributed by the signaldistribution unit 2; and a control PC 6 for controlling the selection oftest parameters and various analytical operations, and the use of the PCtester provides the following advantages:

[0119] (1) The objects of observation that may be memory chips, TSOPs orTCP having a package structure and comprising memory chips, memorymodules such as DIMMs having a module structure and comprising suchpackages, memory module having a module structure and comprising memorychips or PCs mounted by memory modules can be can be tested inquasi-operating conditions that are very close to the actual operatingconditions.

[0120] (2) It is possible to realized a high performance PC tester atlow cost by utilizing a measurement PC unit 1 mounted by a memory moduleto be used as reference that may be a DIMM 61.

[0121] (3) Memory chips, unit products, memory modules and PCs can betested by means of a same test apparatus.

[0122] (4) As to personal computers expected to have only a shortservice life because of early model changes, it is possible to handle itsimply by selectively using a measurement PC 8 in a measurement PC unit1.

[0123] (5) It is possible to test PCs in quasi-operating conditions,including the performance of the related peripheral circuits of thepersonal computer on which it is to be mounted and the influence ofprocessing operations of the PC using programs that could hitherto giverise to problems when mounting it on the PC.

[0124] (6) A number of memory chips, unit products, memory modules orpersonal computers can be tested simultaneously by using a plurality ofPFBs 3.

[0125] (7) Since the PC tester can be applied to the step of sortingmemory chips, unit products or memory modules, the step of carrying outan acceptance test on memory chips or unit products and/or the step ofcarrying out an acceptance inspection on memory modules, the high speedtester that has hitherto been used for them can be replaced by a testapparatus according to the invention to reduce the investment for thetest, the inspection and the manufacturing equipment.

[0126] (8) Since products to be tested can be sorted underquasi-operating conditions, it is possible to improve the quality ofmemory chips, unit products, memory modules and personal computers.

[0127] While the invention of the inventor is described above in termsof a specific embodiment, the present invention is by no means limitedto the above embodiment, which may be modified and altered in variousdifferent ways without departing from the scope of the invention.

[0128] For example, while the above embodiment is described in terms ofpackages such as TSOPs or TCPs and memory modules such as DIMMs, thepresent invention is not limited thereto and may be equally applied topackages such as TQFPs (thin quad flat packages) and modules such asSIMMs (single in-line memory modules).

[0129] While the control circuit comprises ASICs in the aboveembodiment, the present invention is by no means limited thereto andthey may be replaced by field programmable ICs such as FPGAs. In otherwords, ASICs may include field programmable ICs.

[0130] Additionally, the present invention can effectively be used notonly for SD-RAMs but also other memory products such as DRAMs and flashmemories. Furthermore, the present invention can be applied to logicproducts comprising microcomputers and/or ASICs (including FPGAs).

[0131] The number of distribution substrates and that of PFBs are notlimited to the above description and any appropriate number may be useddepending on the number of products to be tested simultaneously.

[0132] Finally, while the present invention is described in terms ofpersonal computers, the present invention is by no means limited theretoand can equally be applied to information processing apparatus andelectric home appliances having an information processing feature thatare equipped with some other computer, a CPU, memories and/or a controlcircuit and adapted to control the CPU and the memories by means of thecontrol circuit.

What is claimed is:
 1. A method of testing a memory device by using adata processing unit having a memory device mounted thereon, said methodcomprising: a step of supplying a memory device to be tested with asignal to be supplied said memory device; and a step of checkingrelationship between output signals produced from said memory device andoutput signals produced from said memory device to be tested.
 2. Themethod of testing a memory device according to claim 1, wherein: aplurality of said memory devices to be tested are to be tested and saidsignals are supplied in parallel to said plurality of memory devices tobe tested.
 3. The method of testing a memory device according to claim1, wherein: said data processing unit has a control circuit connected tosaid memory device, said control circuit controlling an operation ofsaid memory device.
 4. The method of testing a memory device accordingto claim 1, wherein: said checking step is adapted to check said outputsignals for agreement/disagreement.
 5. The method of testing a memorydevice according to claim 1, wherein: said signals to be supplied tosaid memory device include an address signal, a data signal, a clocksignal and a control signal.
 6. The method of testing a memory deviceaccording to claim 1, wherein: said signals supplied to said memorydevice to be tested is transferred by means of a pipeline system.
 7. Themethod of testing a memory device according to claim 2, wherein: saidsignals supplied in parallel to said plurality of memory devices to betested are transferred by means of a pipeline system.
 8. The method oftesting a memory device according to claim 7, wherein: said signalssupplied by means of said pipeline system are distributed in a pluralityof stages and supplied in parallel to said plurality of memory devicesto be tested.
 9. A method of manufacturing a memory device comprising: astep of forming a semiconductor device having a memory; and a step ofsupplying said memory of said semiconductor device with signals to besupplied to a first memory mounted on a data processing unit andchecking relationship between signals output from said first memory andsignals output from said memory of said semiconductor device.
 10. Themethod of manufacturing a memory device according to claim 9, wherein: aplurality of said memories used in said step of forming saidsemiconductor device are to be formed and said signals to be supplied tosaid first memory are supplied in parallel to said plurality of memoriesused in said step of forming said semiconductor device.
 11. The methodof manufacturing a memory device according to claim 9, wherein: saiddata processing unit is coupled to said first memory and has a controlcircuit for controlling an operation of said first memory.
 12. Themethod of manufacturing a memory device according to claim 9, wherein:said checking step is adapted to check said output signals foragreement/disagreement.
 13. The method of manufacturing a memory deviceaccording to claim 9, wherein: said signals to be supplied to said firstmemory include an address signal, a data signal, a clock signal and acontrol signal.
 14. An apparatus for testing a memory device, saidapparatus comprising: a socket to be mounted with a memory device to betested; a terminal supplied from a data processing unit mounted with amemory with signals to be supplied to the memory and output signals ofsaid memory; and a control section for determining relationship betweenthe output signals of from said socket and the output signals from saidmemory.
 15. The apparatus for testing a memory device according to claim14, further comprising: a first board for carrying said socket to bemounted with said memory device to be tested; and a second board adaptedto carrying a plurality of said first boards, distribute the signals tobe supplied to said memory and supply the signals to said memory deviceto be tested.
 16. The apparatus for testing a memory device according toclaim 15, wherein: the apparatus comprises a plurality of types of saidfirst boards to accommodate said memory device to be tested.
 17. Theapparatus for testing a memory device according to claim 16, wherein:said memory device to be tested is a TSOP or a TCP.
 18. The apparatusfor testing a memory device according to claim 14, wherein: a pluralityof said memory devices to be tested are to be tested and said signals tobe supplied to said memory are supplied in parallel to said plurality ofmemory devices to be tested.
 19. The apparatus for testing a memorydevice according to claim 14, wherein: said data processing unit iscoupled to said memory and comprise a control connector for controllingan operation of said memory.
 20. The apparatus for testing a memorydevice according to claim 14, wherein: said control circuit is adaptedto check said signals for agreement/disagreement.
 21. The apparatus fortesting a memory device according to claim 14, wherein: said signals tobe supplied to said memory include an address signal, a data signal, aclock signal and a control signal.
 22. The apparatus for testing amemory device according to claim 14, further comprising: a substrate fortaking out signals from the memory mounted on said data processing unitand supplying them to said terminal.
 23. A method of testing a memorymodule by using a data processing unit mounted with a memory modulehaving a plurality of memory devices, said method comprising: a step ofsupplying a memory device to be tested with signals to be supplied tosaid memory module; and a step of checking the relationship betweenoutput signals from said memory module and output signals from saidmemory device to be tested.
 24. The method of testing a memory moduleaccording to claim 23, wherein: said signals to be supplied to saidmemory module are signals to be supplied to a first memory device ofsaid plurality of memory devices and said output signals from saidmemory module are the output signals from a second memory device of saidplurality of memory devices.
 25. The method of testing a memory moduleaccording to claim 24, wherein: said first memory device and said secondmemory device may be a same memory device.
 26. The method of testing amemory module according to claim 23, wherein: a plurality of said memorydevices to be tested are to be tested and said signals to be supplied tosaid memory module are supplied in parallel to said plurality of memorydevices to be tested.
 27. The method of testing a memory moduleaccording to claim 23, wherein: said data processing unit is coupled tosaid memory module and has a control circuit for controlling anoperation of said memory module.
 28. The method of testing a memorymodule according to claim 23, wherein: said checking step is adapted tocheck said output signals for agreement/disagreement.
 29. The method oftesting a memory module according to claim 23, wherein: said signals tobe supplied to said memory module include an address signal, a datasignal, a clock signal and a control signal.
 30. The method of testing amemory module according to claim 23, wherein: said memory device to betested is one of a plurality of memory devices mounted on memory module.31. A method of manufacturing a memory module comprising: a step ofpreparing a memory device; a step of supplying said memory device, froma data processing unit mounted with a first memory, with signals to besupplied to the first memory and checking relationship between outputsignals from said first memory and output signals from said memorydevice; and a step of forming the memory module by mounting on asubstrate said memory device checked for the relationship in thepreceding step.
 32. The method of manufacturing a memory moduleaccording to claim 31, wherein: a plurality of said memory devices areprepared and said signals to be supplied to said first memory aresupplied in parallel to said plurality of memory devices.
 33. The methodof manufacturing a memory module according to claim 31, wherein: saiddata processing unit is coupled to said first memory and has a controlcircuit for controlling an operation of said memory module.
 34. Themethod of manufacturing a memory module according to claim 31, wherein:said checking step is adapted to check said output signals foragreement/disagreement.
 35. The method of manufacturing a memory moduleaccording to claim 31, wherein: said signals to be supplied to saidfirst memory include an address signal, a data signal, a clock signaland a control signal.
 36. An apparatus for testing a memory module, saidapparatus comprising: a board to be provided with a memory module havinga plurality of memory devices; a terminal supplied from a dataprocessing unit mounted with said memory module with signals to besupplied to the memory module and with output signals of said memory;and a control section for supplying said board with signals to besupplied to said memory module, and for determining relationship betweenoutput signals from said board and output signals from said memorymodule.
 37. The apparatus for testing a memory module according to claim36, wherein: said signals to be supplied to said memory module aresignals to be supplied to a first memory device of said plurality ofmemory devices and said output signals from said memory module areoutput signals from a second memory device of said plurality of memorydevices.
 38. The apparatus for testing a memory module according toclaim 37, wherein: said first memory device and said second memorydevice may be a same memory device.
 39. The apparatus for testing amemory module according to claim 36, wherein: said signals to besupplied to said memory module are supplied in parallel to saidplurality of memory devices.
 40. The apparatus for testing a memorymodule according to claim 36, wherein: said data processing unit iscoupled to said memory module and has a control circuit for controllingthe operation of said memory module.
 41. The apparatus for testing amemory module according to claim 36, wherein: said control section isadapted to check said output signals for agreement/disagreement.
 42. Theapparatus for testing a memory module according to claim 36, wherein:said signal to be supplied to said first memory include an addresssignal, a data signal, a clock signal and a control signal.
 43. Theapparatus for testing a memory module according to claim 36, wherein:said apparatus for testing a memory module is adapted to define a testunit on said board.
 44. The apparatus for testing a memory moduleaccording to claim 43, wherein: one of said plurality of memory devicesmounted on said memory module to be provided on said board is tested.45. A method of manufacturing a computer comprising: a step of preparinga mother board carrying a CPU, a socket to be mounted with a memorydevice to be tested and a control circuit connected to said CPU and saidsocket; a step of preparing a memory module having a plurality of memorydevices; and a step of arranging said memory module on said socket; saidmemory devices of said memory module satisfying a predeterminedrelationship in a test step; said test step being adapted to supply saidmemory devices, from a data processing unit mounted with a first memory,with signals to be supplied to said first memory, and adapted to checkrelationship between output signals from said first memory and outputsignals from said memory devices.
 46. The method of manufacturing acomputer according to claim 45, wherein: said signals to be supplied tosaid first memory are supplied in parallel to said plurality of memorydevices.
 47. The method of manufacturing a computer according to claim45, wherein: said data processing unit is coupled to said first memoryand has a control circuit for controlling an operation of said firstmemory.
 48. The method of manufacturing a computer according to claim45, wherein: said checking step is adapted to check said output signalsfor agreement/disagreement.
 49. The method of manufacturing a computeraccording to claim 45, wherein: said signals to be supplied to saidfirst memory include an address signal, a data signal, a clock signaland a control signal.
 50. A method of testing a memory module having adata processing unit provided with a DIMM carrying a plurality of memorydevices, said method comprising; a step of supplying said memory devicesto be tested with signals to be supplied said DIMM: and a step ofchecking relationship between output signals produced from said DIMM andoutput signals produced from said memory devices to be tested.
 51. Amethod of manufacturing a memory device comprising: a step of preparinga memory device; a step of supplying said memory device from a dataprocessing unit carrying a first memory with signals to be supplied tosaid first memory and checking relationship between signals output fromsaid first memory and the signal output from said memory device; and astep of forming a DIMM by mounting on a substrate the memory devicechecked in the above step for a predetermined relationship.
 52. Anapparatus for testing a memory module, said apparatus comprising: aboard to be provided with a DIMM carrying a plurality of memory devices;a terminal supplied from a data processing unit mounted with a DIMM withsignals to be supplied to the DIMM and with output signals from saidDIMM; and a control section adapted to supply said board with saidsignals to be supplied to said DIMM for determining relationship betweenoutput signals from said board and output signals from said DIMM.
 53. Amethod of manufacturing a computer comprising: a step of preparing amother board carrying a CPU, a socket to be mounted with a DIMM, and acontrol circuit connected to said CPU and said socket; a step ofpreparing a DIMM carrying a plurality of memory devices; and a step ofarranging said DIMM on said socket; said memory devices of said DIMMsatisfying a predetermined relationship in a test step; and said teststep being adapted to supply said memory devices with signals from adata processing unit mounted with a first memory, said signals being tobe supplied to said first memory, and adapted to check relationshipbetween output signals from said first memory and output signals fromsaid memory devices.